CPLD Tutorial
Originally Posted by acondit
Reply with QuoteThe present Tutorial in this link.
http://www.cnczone.com/forums/showthread.php?t=74497
Will be moved to here for a new exposure.
Mariss gave his blessing
About the Verilog tutorial I promised:
I'm now ready to take a crack at this. It will cover what I have learned as a non-programmer in the past 18 months or so going from zero to now with Verilog and CPLDs.
I was afraid of Verilog and wasted about 2 years avoiding it until I had no choice. I thought it would be formidable to learn and learning always makes my head hurt. Verilog can be formidable because it is a powerful tool if it is used to its full potential. I found out it can be used easily if the applications are relatively simple such as mine are. Dirt-simple and painless actually for small CPLDs.
I'm not a programmer and I do not like programming. Just so you know; for me code has always been a means to end and has never been something to be enjoyed for its own sake. I reserve analog design as "something to be enjoyed for its own sake".
The assumption here (prerequisites?) is you already know how to design logic. You have to know how to generate timing charts, be comfortable with accounting for propagation delays, know Karnaugh Maps and generally be really conversant with efficient logic design. If you're not, I really can't help you there because the effort to bring you up to speed is beyond the scope of this exercise.
Real programmers are going to blanch at what follows. Most will wonder where I got the nerve to do a Verilog tutorial when I know next to nothing about it. Trust me, it works though. It isn't meant as an "in your face" thing at all. I know and respect many top-notch programmers. Rather, it is how do you efficiently convert a logic diagram into a small CPLD and be assured it will work properly right away. It is a very narrow venue.
There are only 6 things you have to learn in Verilog to make anything you want to work that will fit in a 32 or 64 macrocell CPLD:
1) Declare inputs and outputs. They are the gozinto and gozoutof pins on your CPLD. They come directly after the top module name.
(input INA, INB, INC, etc, output OUTX, OUTY, OUTZ, etc, inout SOMENAME);
2) Write behavioral descriptions for your D-Flops and counters. These are subroutines. I put them after the top module.
Here's one for a very simple D-Flop:
module DF (input C, D, output Q);
reg df = 0;
always @(posedge C)
df <= D;
assign Q = df;
endmodule
Here's one for an Up-Down counter:
module CB12BRE (input UD, CE, R, C, output [11:0] Q);
reg [11:0] u_d = 12'h000;
always @(posedge C)
if (R)
u_d <= 12'h000;
else if (CE)
if (UD) begin
u_d <= u_d + 1;
end
else begin
u_d <= u_d - 1;
end
assign Q = u_d;
endmodule
3) Anytime you have a counter, name it and declare a wire:
wire [11:0] QB; means you have a 12-bit bus named 'QB' belonging to some counter named 'QB'.
4) "Solder in" your D-Flops and counters:
DF F1 (.C(CLK), .D(STP), .Q(Q1));
Which means module named DF (a subroutine), here called 'F1' has its clock (C) connected to a global signal named 'CLK' which happens to be the oscillator. The flop's 'D' input here happens to connect to a signal named 'STP'. It's output 'Q' is named 'Q1' to distinguish itself from all the other D-flops in the circuit.
Same goes for:
CB12BRE M1 (.C(CLK), .CE(So), .UD(Do), .R(Q12), .Q(QB));
Which is our 12-bit counter subroutine here named M1 whose C input goes to CLK, it's CE (clock enable) goes to a signal called 'So', its UD input (up-down) goes to something called 'Do' and its R (reset) input goes to some D-flop named 'Q12'. The 12-bit counter's outputs are named 'QB' and reference the named wire 'wire [11:0] QB'.
5) Everything else is an 'assign' statement:
assign G11 = G9 & and G10;
Means "The output of gate 11 is the AND combination of gates 9 and 10". Only 4 operators here; & = AND, | = OR, ^ = XOR and ~ = invert.
6) All designs are fully synchronous. That means if it has a CLK input (C), it goes to the system clock. You do not have access to any counter or D-flop clock. This seems like a terrible restriction but it's not. You have the CE (clock enable) inputs which more than makes up for the restriction as you will see later.
That's it. Those are the 6 things you have to learn to do what you need.
This is the CNCzone, electronics forum. What I propose as a learning project is to make a 7A, 80V half-step drive. Squeeze into a $1 CPLD the logic and make a practical and usable chopper-type (constant off-time) drive as a design exercise. We will go from a description of what's required, generate a logic schematic, minimize the logic and optimize it for a CPLD and translate it into Verilog code. Should some care to build it, it will work better than what's out there commercially.
I think it will be a lot of fun. Everyone will learn something and a few will get hooked. I need to know if there is an interest because it will place a burden on my time to prepare the material.
Mariss
